The ramp generation function can be done using the direct digital synthesis (DDS) technique or using a phase locked loop (PLL) with variable reference frequency or variable voltage controlled oscillator (VCO) division ratio. The DDS approach requires a high performance DAC and smoothing filter, which makes it very difficult to build when high output frequencies and large variations are required.
Higher output frequencies can be generated using a PLL with a variable reference frequency, which is typically generated with a low frequency DDS, but since the PLL amplifies the spurs generated by the DDS by 20*log(N)—where N is the ratio of the VCO to the reference frequency, the DDS design becomes again very critical.
The latter approach, using an integrated PLL-based fractional frequency synthesizer with externally controlled VCO division ratio, is prone to introduce digital switching noise and add cost and complexity to the system. In the prior art case where a fractional N synthesizer is used with an external ramp controller, real time transfers of the frequency word are required to the PLL. This is problematic as it causes digital switching noise while the synthesizer is running, and it also uses more power in the inter-chip transactions and costs more than an integrated approach. Also the rate of change of the frequency may be limited by the serial port transfer speed, resulting in a less smooth ramp. One known method to generate a low frequency ramp, or ‘chirp’, signal is to use an all digital technique using a direct digital synthesizer (DDS), such as that used by Parkes (U.S. Pat. No. 5,311,193 1994). This idea is commonly extended to high frequencies by using the DDS as the reference for an integer PLL using a method such as Gilmore, (U.S. Pat. No. 4,965,533 1990). Both the low frequency and the high frequency methods of Parkes and Gilmore rely on a DDS based solution which has problems in that the all digital process can create many unwanted spurious signals when converted back to analog. Also the hardware complexity is significantly larger. Further the idea is restricted as the bandwidth of the PLL should be relatively narrow to reduce the DDS spurs, which creates larger linearity distortions at ramp start or stop. Another method disclosed in Gaskel et al. (U.S. Pat. No. 5,079,521 1992) uses a fractional synthesizer to generate frequencies of arbitrary values. Another common method to generate a ramped frequency at high carrier frequencies is to directly drive a VCO using a programmable voltage generator based on a high resolution DAC. This approach creates calibration problems due to the non-linear tuning characteristic of the VCO, cannot truly achieve linear frequency sweeps and is generally not suitable for large volume semiconductor manufacturing due to the difficulties in controlling the analog parameters involved in the ramp generation. This is especially true when large sweeps are needed or large temperature variations are encountered. All this prior art is incorporated herein by this reference.